Vol. 3, Issue 1 (2018)
An improved carry save adder design
Author(s): S Subha
Abstract: Binary addition is performed using full adders. Carry save adders are studied in literature and have wide applications in numerical applications. This paper proposes binary addition algorithm. The input is two 32-bit numbers. The sum and carry of individual bits are calculated. The results are added according to weightage to the bits using modified full adder logic. The result is n+1 bit number. The proposed model is simulated with Quartus2 toolkit and compared with carry save adder logic. An improvement in area by 27% with power saving of 8.5% with timing improvement of 6.8% in proposed model compared with traditional model is observed.