The multifaceted nature of Finite Impulse Response (FIR) channel is commanded by the quantity of adders or sub tractors which are utilized to actualize the co-proficient multipliers. A Common Sub-Expression Elimination (CSE) calculation depends on the Canonical Signed Digit (CSD) portrayal of channel co-efficient for actualizing low intricacy FIR channels. Here, decrease of multiplier in straight stage FIR channels is accomplished by changing over the multiplier co-efficient to Minimum Signed Powers-of Two (MSPT) or Canonical Signed Digit (CSD) portrayal of the multiplier. This multiplier can be actualized utilizing a progression of movements and augmentations or deductions. The CSE calculation is utilized to discover and dispose of increasingly regular sub-expressions among channel co-efficient which brings about force and region sparing while actualized in FIR filters. The Common Sub-Expression Elimination (CSE) technique to be utilized for the VLSI configuration will bring about decreased multiplier in Finite Impulse Response (FIR) channel with few adders and registers.